A semiconductor integrated circuit technology has rapidly progressed. For example, in the case of dynamic memory, memory chips with a capacity of 1 though 4 Mbit have been already put into mass production and ultra large integration memory chips such as 16 Mb or 64 Mb memory are now being developed. Such an ultra large integration technology is applied to a logic circuit as well as a memory circuit, and a variety of functional logic integrated circuits represented by 32 bit CPU or 64 bit CPU are also under development.
In these logic circuits, an arithmetic operation is carried out by using digital signals, i.e., binary signals composed of 1 and 0. For example, a Neumann method is adopted for a computer, where commands are executed one by one according to a predetermined program. Although simple numerical calculations can be carried out at very high speed by this method, it takes a lot of time to perform the pattern recognition or image processing. Furthermore, this method is not suitable for information processing such as association of ideas, memorizing and learning, which is mankind's strongest point. In spite of a lot of research and development activities for software technology, notable results have not been produced yet.
There has been another stream of research to get rid of these difficulties at once and then to construct a computer which imitates arithmetic operations of the brain, i.e., neuron circuit computer (neural computer) by studying a brain function of a living things. This kind of research began in 1940s and becomes very active in last several years based on the fact that the progress in LSI technology may make it possible to realize the hardware of neuron computer.
However, the present semiconductor LSI technology still has too many problems to put it into practice. This is described more concretely. For example, in order to make the hardware with the function of one human neuron cell (neuron), a circuit must be constructed by combining a lot of semiconductor elements. In other words, it is very difficult to construct the practical number of neurons on a semiconductor chip.
The main purpose of this invention is to provide a semiconductor device which realizes the function of a neuron using a single MOS type semiconductor element. Before detailed explanation of this invention is described, what function is requested for one neuron and what difficulties take place when constructing neuron using current technologies are described.
FIG. 19 is a schematic representation illustrating the function of a neuron cell, i.e., neuron, which was proposed by McCumllock and Pitts as a mathematical model of neuron (Bull. Math. Biophys., Vol. 5, p. 115 (1943)). At present, the studies are being carried out actively to construct a neuron computer by realizing this model with semiconductor circuits. V.sub.1, V.sub.2, V.sub.3, . . . , V.sub.n are n input signals defined as, for example, magnitudes of voltages, and correspond to signals transferred from another neurons. W.sub.1, W.sub.2, W.sub.3, . . . , W.sub.n are coefficients representing the coupling strength between neurons, and are biologically called synapse coupling. The function of this neuron is simple. When the value Z, linear sum of the product of each input V.sub.i and weight W.sub.i (i=1-n), becomes larger than a predetermined threshold value V.sub.TH *, the neuron outputs 1; on the other hand, 0 when Z is less than V.sub.TH *. The numerical expression is as follows: ##EQU1##
FIG. 19(b) shows the relationship between Z and V.sub.out. The output is 1 when Z is large enough as compared with V.sub.TH *, and 0 when Z is small enough.
Next, an example of the circuits to realize the above-mentioned function using conventional semiconductor technology is shown in FIG. 20. In the figure, 102-1, 102-2 and 102-3 denote operational amplifiers. FIG. 20(a) shows a circuit to obtain Z by adding the product of input signal V.sub.i (i=1-n) and weight Wi. I.sub.i denotes electric current flowing through R.sub.i. From I.sub.i =V.sub.i /R.sub.i, ##EQU2## the output voltage V.sub.a of the operational amplifier 102-1 is given by ##EQU3## Since I.sub.b is given by -V.sub.a /R, I.sub.a and I.sub.b have the same magnitude (I.sub.a =I.sub.b) and the opposite direction of flow, leading to the expression: ##EQU4## By the comparison between Eqs. (1') and (4'), the weight coefficient W.sub.i is found to be R/R.sub.i and therefore determined by the resistance. The circuit shown in FIG. 20(a) is a circuit to generate the voltage representing the linear sum of input signals obtained by summing up electric currents. FIG. 20(b) is an example of circuit to convert the value of Z into V.sub.out, where Z is connected to a non-inversion input terminal of operational amplifier 102-3. Since an operational amplifier is an amplifier having a large voltage amplification (gain), V.sub.out =V.sup.+ when Z&gt;E.sub.0 and V.sub.out =V.sup.- when Z&gt;E.sub.0, as shown in FIG. 20(c). Here, V.sup.+ and V.sup.- are the maximum and the minimum values of outputs which are determined by power supply voltage supplied to the operational amplifier. The value of V.sub.TH * can be changed by varying the voltage E.sub.0 applied to non-inversion terminal. One of the problems of the circuit shown in FIGS. 20(a) and (b) is such that a lot of semiconductor elements are required to construct a neuron. Three operational amplifiers are used in the circuit of the figure and therefore 30 transistors are necessary since at least 10 transistors are usually required to construct one operational amplifier. And since the sum operation is made on the basis of electric current mode, a large amount of current always flow, resulting in large power dissipation. Namely, one neuron not only occupies a large area on a chip but also dissipates much power. Therefore it is difficult to attain large scale integration. Even if large scale integration can be attained by shrinking the dimensions of transistor, it is almost impossible to construct a practical integrated circuit because of high density of the power dissipation.
The present invention has been made in order to solve such problems as mentioned above and to provide a semiconductor device which realizes the function of one neuron with a single element and a neuron computer chip having a high integration density and low power dissipation characteristics.